The Tiny Tera: A Packet Switch Core
نویسندگان
چکیده
In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a highperformance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf technology, we plan to demonstrate that a very highbandwidth switch can be built without the need for esoteric optical switching technology. By employing novel scheduling algorithms for both unicast and multicast traffic, the switch will have a maximum throughput close to 100%. Using novel highspeed chip-to-chip serial link technology, we plan to reduce the physical size and complexity of the switch, as well as the system pin-count.
منابع مشابه
The Tiny Tera:1 A Packet Switch Core
In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a highperformance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf technology, we plan to demonstrate that a very highb...
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We would like to thank Adisak Mekkittikul for help and numerous discussions about the scheduler design, particularly with the pipelining technique described on page 2. 11 References [1] http://tiny-tera.stanford.edu/tiny-tera [2] N.McKeown, " Scheduling Cells in an input-queued switch, " PhD Thesis,
متن کامل6 . 3 Preprocessing the input vector
We would like to thank Adisak Mekkittikul for help and numerous discussions about the scheduler design, particularly with the pipelining technique described on page 2. 11 References [1] http://tiny-tera.stanford.edu/tiny-tera [2] N.McKeown, " Scheduling Cells in an input-queued switch, " PhD Thesis,
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عنوان ژورنال:
- CoRR
دوره cs.NI/9810006 شماره
صفحات -
تاریخ انتشار 1997